JPEG Encoder FPGA Implementation

I have been working as a system engineer on video coding for a long time. Here are what a video system engineer often does.

1. Read the standard specification MANY times,
2. Optimize the encoder and decoder implementation,
3. Develop system architecture,
4. Write C model, which is a software to model the system architecture.

Based on system architecture, HW engineer will develop micro-architecture of certain components and write HDL (verilog or VHDL) to implement them in ASIC or FPGA. Software or firmware engineer will write driver to utilize the HW modules, and provide high level API for application developers.

In the post, I will use a simple image coding standard, JPEG, as an example to show the complete design flow from specification to HW implementation in FPGA.

Verilog is the language of choice for HW implementation. The usage of verilog may seem to be unconventional to veteran ASIC designer. However, I think that's good enough for a system engineer.

1. JPEG encoder software

2. Architecture

3. HDL implementation

4. Simulation

5. FPGA implementation

6. Source code and copyright