An ethernet based FPGA emulation environment

After all the simulations and debugging efforts, we hope the design will work on FPGA. Isn't that promised by the beauty of synchronous design, and the magic of the EDA tools? Unfortunately the design may not work properly, so we need to debug.

One debugging approach is to do this on HW using logic analyzer. Connect the outputs that need to be observed to external pins, and connect these pins to logic analyzer. The logic analyzer will display the data on these pins, and the developer will compare these data with expected values and figure out where the problem is. This is usually an iterative process in order to narrow down exactly which logic causes the problem.